Principal Design Verification Engineer- SerDes/PHY IP at Astera Labs

Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of high-speed SerDes/PHY IP for rack-scale AI infrastructure. The role involves architecting UVM-based verification environments, developing SystemVerilog/UVM testbenches, driving coverage closure, verifying PHY behavior against PCIe, UALink, UCIe, and Ethernet standards, and collaborating with analog/mixed-signal, digital, SoC, firmware, and customer engineering teams. The position requires a bachelor's degree in a relevant engineering field, at least 8 years of design verification experience, and expert proficiency in SystemVerilog and UVM. The salary range is $207,000 to $230,000, with possible discretionary bonus, incentives, and benefits.