Description
The Pune MCU team DFT Lead will architect DFT design, manage DFT instrument insertion and simulation, and deliver DFT implementations across SOC, IP, and production. The role collaborates with SOC, IP, DV, BE, and test teams; defines scan, MBIST, JTAG, and functional testing structures; creates or oversees test vectors; closes timing in DFT mode; signs off on DFT requirements; brings up test patterns on silicon; and guides junior DFT engineers. The minimum qualification is a BE/MS degree in Electronics, Electrical, or Computer Engineering with at least 12 years of DFT experience, along with expertise in Mentor/Synopsys test generation tools and complex SOC TO and production DFT.
