Principal DFT Engineer at Synopsys

Synopsys is hiring an ASIC DFT Technical Lead in Bangalore to lead scan insertion and ATPG flows for complex IP designs, collaborate with RTL and verification teams, resolve DFT issues using Spyglass DFT and scan STA tools, apply AI tools to automate DFT tasks, and improve testability, reliability, and design flows. The role requires a BS/MS in Electrical Engineering or Electronics and Communication Engineering, at least 8 years of relevant experience, and prior technical leadership of DFT execution for IP projects.