Description
Astera Labs is hiring a Principal Digital Design Engineer to develop micro-architecture and front-end circuit design for high-performance network controllers. The role covers RTL, synthesis, IP integration, block-level verification, timing closure, DFT, silicon bring-up, and full-chip or block ownership through GDS. Candidates need an electrical engineering background, at least eight years of SoC or silicon product experience, knowledge of high-speed protocols, and experience with Synopsys or Cadence digital design flows. The base salary is $185,000 to $230,000 USD.
