Compensation
$185,000 – $230,000/yr
Astera Labs is seeking a Principal Digital Design Engineer to lead the architectural and implementation of next-generation digital designs for high-performance AI connectivity solutions. The role involves owning complex blocks from micro-architecture through silicon bring-up, driving RTL implementation, and collaborating with various teams to ensure production-quality silicon supports PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.
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Silicon-based hardware connectivity solutions and software for rack-scale AI.San Jose, CA, United States
Astera Labs builds silicon-based hardware connectivity solutions and software for rack-scale AI, including smart fabric switches, retimers, memory controllers, and signal conditioners. Astera Labs reported second-quarter 2026 revenue of $392.4 million, up 27% quarter over quarter and 104% year over year.