Description
Astera Labs is hiring a Principal Digital Design Engineer to architect and implement complex digital blocks and subsystems for high-performance connectivity solutions. The role owns micro-architecture and RTL design, collaborates with verification, PD, and DFT teams, leads timing closure and silicon bring-up, mentors junior engineers, and drives designs to production. Candidates need a bachelor’s degree in electrical engineering or equivalent, at least 8 years of hands-on experience developing complex SoC or silicon products in server, storage, or networking markets, and expertise in digital design, high-speed protocols, advanced CMOS production, and silicon bring-up.
