Description
Renesas is hiring an ASIC Digital Design Engineer to develop the digital sections of memory data buffer chips for DDR5, DDR6, and beyond. The role covers Verilog RTL architecture, clocking, FSM, low-power and high-speed design, digital backend design, synthesis, static timing analysis, formal verification, ECOs, and design documentation, while also mentoring junior and New College Grad engineers. The position requires a bachelor's or master's degree in a relevant engineering or computer science field and at least 12 years of ASIC/IC design experience.
