Description
The role develops reusable intellectual property for SoC and subsystem integration, translating system requirements into RTL designs and driving them through silicon. Responsibilities include micro-architecture development, RTL design in Verilog, SystemVerilog, or VHDL, power-performance-area optimization, lint, CDC, synthesis, STA, bug closure, design reviews, and verification collaboration. The position requires strong RTL design experience, SoC/IP integration knowledge, and hands-on experience with lint, CDC, synthesis, and timing analysis; full-cycle IP/SoC development, formal verification, low-power flows, and post-silicon validation are preferred.
