Description
Synopsys is hiring a Principal Verification Engineer to develop testplans, functional coverage models, and reusable SystemVerilog/UVM testbench infrastructure for memory interface IP. The role covers test case creation, firmware and RTL debugging, technical reviews, virtual prototyping and emulation research, and mentoring junior engineers. It requires a relevant bachelor's degree with 12+ years of verification experience, or an MSc with 10+ years, or a PhD with 8+ years, along with strong SystemVerilog/UVM, simulation, waveform, C, co-simulation, assertion-based verification, and Linux skills. The position is based in Ottawa and offers health, wellness, and financial benefits.
