Description
Synopsys is hiring a Principal Digital Verification Engineer to verify memory-interface IP for HBM, DDR, LPDDR, and AMBA protocols. The role involves building SystemVerilog and UVM verification environments, developing test plans and reusable verification IP, driving functional coverage closure, debugging with simulation tools, collaborating with design and architecture teams, and mentoring junior engineers. Candidates need a bachelor's or master's degree in electrical or computer engineering, 8 to 10+ years of ASIC or SoC verification experience, and proven production-level interface-IP verification experience.
