Description
The Digital Verification Engineer will own verification of one or more submodules, including verification IPs and testbenches across integration levels. The role collaborates with architects, discipline leads, and DV teammates on verification strategy, planning, metrics, testbench development, documentation, issue resolution, and process improvement. It requires a master or PhD in electrical or electronic engineering, computer science, or an equivalent field, at least eight years of digital design and verification experience, UVM and System Verilog training, ASIC/SoC flow familiarity, and proficiency with Verilog, UVM, coverage, formal verification, scripting, and version control. The position is full-time in Gratkorn and may involve security-related tasks.
