Compensation
$209,000 – $230,000/yr
Astera Labs is seeking a Principal Emulation Engineer to verify protocols on complex ASICs. The ideal candidate will have experience with communication protocols such as PCI-Express, DDR, Ethernet, or NVMe and be proficient in System Verilog and verification environments. The role involves creating environments for stress-testing ASICs and debugging design issues. A Bachelor’s in EE or Computer Science and 8+ years of experience are required.
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Silicon-based hardware connectivity solutions and software for rack-scale AI.San Jose, CA, United States
Astera Labs builds silicon-based hardware connectivity solutions and software for rack-scale AI, including smart fabric switches, retimers, memory controllers, and signal conditioners. Astera Labs reported second-quarter 2026 revenue of $392.4 million, up 27% quarter over quarter and 104% year over year.