Principal Engineer - ASIC Digital Design (Memory Interface IP- HBM/DDR/LPDDR) at Synopsys

Location: Hyderabad, Telangana
Level: lead/mgmt
Posted: Sep 14, 2026

Description

Synopsys is hiring a Principal ASIC Design Engineer focused on memory interface IP for HBM, DDR, and LPDDR. The role owns complex RTL blocks from architecture through implementation and verification handoff, collaborates with analog and physical design teams, develops verification plans, optimizes timing, power, and area, leads technical reviews, mentors engineers, and interfaces with customer engineering teams. Candidates need 8–10+ years of ASIC digital design experience, expertise in at least two memory interface protocols, production-quality IP experience, strong SystemVerilog and UVM knowledge, and familiarity with AMBA protocols and EDA toolchains.

Required Skills

HBM/DDR/LPDDR
SystemVerilog
UVM
AMBA protocols
Synopsys Fusion Compiler
PrimeTime
DC Compiler
Mixed-signal design

Additional Information

Required Previous Experiences: 8–10+ years of hands-on ASIC digital design experience focused on RTL design and verification
Experience designing and delivering production-quality IP or SoC blocks that have been taped out and validated in silicon
Experience working with AMBA protocols in memory subsystem integration
Proficiency with Synopsys or Cadence EDA toolchains for synthesis, timing analysis, and power optimization
Preferred Qualifications: Deep expertise in at least two memory interface protocols, including HBM, DDR4, DDR5, LPDDR4, or LPDDR5
Strong SystemVerilog RTL design and familiarity with UVM or other verification methodologies
Experience with mixed-signal interface design and collaboration with analog teams