Principal Engineer, ASIC Physical Design at Micron

Department: STPG

Setup: On-site
Location: Minneapolis, Minnesota
Level: senior
Posted: May 20, 2026

Description

Micron Technology is hiring an ASIC Physical Design Engineer to support its DRAM Tester Solutions group. The role leads block-level and full-chip physical design, including floorplanning, placement, CTS, routing, timing, power, signal integrity, and tape-out across advanced technology nodes. Responsibilities also include developing APR flows, scripts, and methodologies for PPA improvements and coordinating closure work with cross-functional teams. The position requires a bachelor’s or master’s degree in a relevant field, at least 15 years of ASIC physical design experience, multiple production tape-outs in advanced process nodes, low-power design expertise, and scripting proficiency.

Required Skills

Physical design
Timing closure
Power integrity
Tcl
Python
UPF/CPF

Additional Information

Minimum Education: Bachelor’s or master’s degree in Electrical Engineering, Electronics, or Computer Architecture, or equivalent experience
Required Previous Experiences: At least 15 years of hands-on ASIC physical design implementation experience
Multiple production tape-outs in advanced process nodes
Low-power design expertise with UPF/CPF and multi-voltage systems
Scripting proficiency in Tcl, Perl, or Python for flow automation
Preferred Qualifications: Experience with Synopsys and Cadence physical design and timing tools
Physical verification closure using Calibre and power integrity analysis tools
IR/EM signoff and resolution at block and full-chip level
Background in memory tester designs, high-speed interfaces, or microprocessor architectures
Experience developing and enabling APR flows for new technology nodes