Description
NXP is seeking a Principal Engineer - Digital IP Verification (G4) to lead end-to-end verification of complex digital IP and subsystems, drive first-pass silicon success, and improve verification quality, coverage, automation, and closure. The role requires 10–15 years of hands-on experience with complex multi-million gate designs, expertise in SystemVerilog/UVM and C/C++, and knowledge of HDLs, simulators, testbench architecture, assertions, coverage, microcontroller architectures, and memory subsystems. The engineer will collaborate with global cross-functional teams and may support pre- and post-silicon validation.
