Principal IP verification engineer at NXP

Location: Bengaluru, Karnataka
Level: staff+
Posted: Jun 16, 2026

Description

The Principal IP Verification Engineer will verify complex memory controllers and interconnects, develop scalable SystemVerilog/UVM verification environments, own end-to-end IP sign-off, achieve functional and code coverage, manage regressions and debug failures, and collaborate with global design and architecture teams. The role requires 10+ years of experience and strong expertise in SystemVerilog, UVM, Verilog, functional verification, assertions, coverage, and interconnect protocols.

Required Skills

SystemVerilog
UVM
Verilog
Functional verification
SVA assertions
Coverage
AXI
AHB
CHI
PCIe
Formal verification

Additional Information

Required Previous Experiences: 10+ years of experience
Strong experience in SystemVerilog, UVM, and Verilog
Functional verification, SVA assertions, and coverage
Interconnect protocols including AXI, AHB, CHI, and PCIe
Debugging complex RTL and testbench issues
Preferred Qualifications: Formal verification experience
Translation Company Name: IN61 NXP India Private Limited