Description
Micron Technology is seeking a senior VLSI layout engineer to lead full-chip floor planning, integration, physical implementation, signoff, and tape-out execution for complex analog, mixed-signal, memory, and high-speed interface designs. The role owns DRC, LVS, ERC, EMIR, reliability, and manufacturability closure; defines layout methodologies; and leverages AI, machine learning, and agentic AI to improve productivity and automation. The engineer will lead cross-functional and global teams, mentor engineers, and drive technical excellence, with requirements including 15+ years of custom layout experience, full-chip program leadership, advanced EDA tool proficiency, and strong Python, SKILL, and Tcl automation expertise.
