Description
Astera Labs is hiring a Principal Logic Design Engineer to lead RTL and microarchitecture development for UALink-based IP and subsystems. The role involves translating protocol and system requirements into scalable hardware architectures, designing high-bandwidth data paths and control logic, developing SystemVerilog RTL, optimizing performance and power, defining interfaces with other SoC components, collaborating with verification and physical design teams, debugging complex issues, and providing technical leadership and mentorship. The position requires 10–15 years of experience in RTL and microarchitecture development, high-speed interconnects or coherent fabrics, computer architecture, networking, data movement, CDC, reset architecture, and hardware design methodology; direct UALink experience and familiarity with PCIe, CXL, CCIX, CHI, or Ethernet are preferred.
