Principal Package Design Engineer at RenesasElectronics

Seniority in posting: senior

Compensation

$200,000 – $240,000/yr

Setup: Hybrid
Location: San Jose, California
Type: Full-time
Level: lead/mgmt
Posted: Sep 26, 2026

Description

Renesas Electronics is hiring a Principal Package Design Engineer to lead advanced semiconductor packaging solutions for high-performance semiconductors and electronic products. The role covers package architecture, flip-chip, wafer-level, panel-level, 2.5D/3D, SiP, and heterogeneous integration technologies; simulation and reliability analysis; OSAT and vendor strategy; assembly flows; qualification; yield improvement; and cross-functional leadership. The position is hybrid at Renesas Electronics America locations in San Jose, California, or Austin, Texas, and offers an annual salary of $200,000-$240,000 plus bonus opportunities.

Required Skills

Semiconductor packaging
Package architecture
Thermal analysis
Reliability testing
CAD simulation
OSAT collaboration
DFM
Package layout

Additional Information

Minimum Education: MSc or PhD in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related field
Required Previous Experiences: 5+ years of experience in advanced semiconductor packaging or advanced electronics packaging and system integration
Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains
Experience with power semiconductor devices and packaging, including Si/SiC/GaN MOSFETs, power modules, and intelligent power modules
Experience with W2W, D2W, D2D 3D heterogeneous integration and chiplet-based packaging
Preferred Qualifications: Master’s or PhD in a relevant engineering discipline
Hands-on experience with Cadence Allegro Package Designer and other package design and simulation tools
Knowledge of JEDEC, IPC, and semiconductor qualification standards
Translation Company Name: Renesas Electronics