Description
Renesas Electronics is hiring a Principal Package Design Engineer to lead advanced semiconductor packaging solutions for high-performance semiconductors and electronic products. The role covers package architecture, flip-chip, chip embedding, wafer-level and panel-level packaging, 2.5D/3D, SiP, BGA/CSP, heterogeneous bonding, simulation, OSAT and vendor strategy, assembly qualification, reliability, yield, and cross-functional leadership. The position is hybrid at Renesas Electronics America locations in San Jose, California, or Austin, Texas, and requires an MSc or PhD in a relevant engineering discipline plus at least five years of advanced semiconductor or electronics packaging and system integration experience.
