Description
The Senior Packaging Engineer will architect and deliver advanced multi‑die IC packages for high‑performance AI accelerators, covering package architecture, substrate design, bump and ball maps, interposer requirements, high‑speed signal routing, power distribution, manufacturability, and vendor engagement with TSMC or OSAT. The role partners with IC design, physical design, SI/PI, and board teams, evaluates emerging packaging technologies, and supports bring‑up, failure analysis, debugging, and qualification. A B.S./M.S. in Electrical Engineering or a related field, multi‑die package design experience, UCIe integration knowledge, and subcontractor-management experience are required.
