Description
Astera Labs is hiring a Principal Package Signal & Power Integrity Engineer to lead the architecture, simulation, optimization, and signoff of electrical performance for high-performance semiconductor packaging and connectivity products. The role covers chiplet, 2.5D/3D, silicon interposer, and heterogeneous multi-die systems, including SIPI modeling, PDN design, high-speed SerDes and PCIe/CXL/Ethernet interfaces, simulation-to-measurement correlation, and cross-functional delivery through production ramps. The position requires 10+ years of relevant experience and offers a base salary of $203,000 to $240,000 USD.
