Principal Physical Design Engineer - Methodology at Astera Labs

Astera Labs is hiring a Principal Physical Design Engineer - Methodology to own and improve reusable physical design flows and automation infrastructure for complex SoC tapeouts. The role focuses on building and maintaining RTL-to-GDSII flows across Cadence and Synopsys toolchains, automating large-scale STA and EMIR runs, and establishing standards, quality checks, and enablement practices. The position requires deep physical design methodology experience, scripting skills, and familiarity with advanced-node semiconductor flows, and it is fully on-site in San Jose, California.