Principal Physical Design Engineer, STA at Astera Labs

Astera Labs is hiring a Principal Physical Design Engineer (STA) to own timing closure from RTL through sign-off for complex connectivity ASICs. The role covers SDC constraints, I/O timing budgets, advanced sign-off at TSMC 7nm and below, ETM libraries, large-scale STA automation, ECO generation, and full-chip timing convergence with RTL, physical design, and verification teams. The position is fully on-site and in-person, requires at least 10 years of timing analysis and sign-off experience, and offers a base salary of USD 209,000.00 to USD 250,000.00.