Principal RTL Design at Micron

Department: DTPG

Setup: On-site
Location: Boise, Idaho
Level: lead/mgmt
Posted: Jun 3, 2026

Description

Micron Technology is hiring a Principal RTL Design Engineer in Boise, Idaho to lead the full RTL design lifecycle for DRAM digital and mixed-signal IP. The role owns architecture, implementation, signoff, power, performance, and area optimization, and collaborates with physical design, verification, and architecture teams. Candidates need a master’s degree in Electrical Engineering with 8+ years of experience or a bachelor’s degree with 10+ years of pre-silicon RTL design experience, along with expertise in ASIC low-power design, Verilog/SystemVerilog, synthesis, verification, and static timing analysis.

Required Skills

RTL design
DRAM IP
Low-power design
Verilog/SystemVerilog
Logic synthesis
Functional verification
Static timing analysis
UPF power intent

Additional Information

Minimum Education: Master’s degree in Electrical Engineering, or Bachelor’s degree with 10+ years of pre-silicon RTL design experience
Required Previous Experiences: 8+ years of experience for the master’s-degree path
10+ years of pre-silicon RTL design experience for the bachelor’s-degree path
Ownership of complex RTL/IP development from micro-architecture through physical design
Experience with ASIC low-power design methodologies, UPF-based power intent, and power-aware CDC/RDC
Preferred Qualifications: Extensive background in DRAM or other memory compose architectures and development
Deep knowledge of CDC, RDC, STA, and low-power techniques in advanced ASIC technology nodes
Experience designing complex digital logic and/or mixed-signal-interfacing circuits
Familiarity with CMOS digital and analog-integrated circuit concepts and their system-level impact
Excellent interpersonal skills and ability to influence multi-functional teams and provide technical leadership