Description
Ambiq is hiring a Principal RTL Engineer to own pre-tapeout quality for digital SoC modules on its MCU platforms and drive architecture, microarchitecture, and RTL development for next-generation silicon. The role involves developing Verilog/SystemVerilog RTL, integrating third-party IP, collaborating with verification, FPGA, and physical design teams, and managing LINT, CDC, RDC, silicon bring-up, and validation quality. The position requires a bachelor’s degree in a relevant engineering field and 20 years of experience, along with deep knowledge of SoC design technologies and the ability to architect and lead technical programs.
