Description
Astera Labs is hiring a Principal Digital Design Engineer to architect and implement complex digital blocks and subsystems for high-performance AI connectivity solutions. The role owns micro-architecture and RTL implementation, drives timing closure and DFT, leads verification and third-party IP integration, supports silicon bring-up, and mentors junior engineers. Candidates need a bachelor's degree in electrical engineering or equivalent, at least 10 years of experience developing complex SoC or silicon products in server, storage, or networking markets, expertise in high-speed protocols and advanced CMOS design flows, and production experience with nodes better than 7nm. The salary range is $185,000 to $230,000, with possible discretionary bonus, incentives, and benefits.
