Description
The Switch Design Verification Engineer will verify complex switch designs by creating SystemVerilog-based verification environments, testbenches, checkers, transactors, and test plans for RTL and gatesim designs at block and chip levels. The role also involves creating ATE testing vectors and C-based diagnostic tests for silicon. Candidates need a master's degree in Electrical and Electronic Engineering, Computer Science, or an equivalent field, at least six years of design verification experience, strong verification and programming skills, and knowledge of SystemVerilog and scripting languages; UVM methodology and networking and switching knowledge are preferred. The position offers an annual base salary of $108,000 to $172,800, a discretionary bonus, equity, and medical, dental, and vision benefits.
