Description
Synopsys is hiring an R&D Engineering Engineer to develop and optimize timing-aware multi-FPGA partitioning algorithms and backend C/C++ components for the ZeBu emulation compile flow. The role focuses on improving partition quality, robustness, and reproducibility by combining graph/hypergraph partitioning, analytical optimization, and constraint-aware approaches for logic, memory, connectivity, and timing constraints. The engineer will collaborate with FPGA P&R and runtime teams on validation and ZeBu platform sign-off, working within a backend software R&D team in Linux/Unix environments.
