Description
Synopsys is hiring an R&D Engineer to develop and optimize timing-aware, constraint-aware multi-FPGA partitioning algorithms for the ZeBu emulation compile flow. The role focuses on improving partitioning robustness, reproducibility, and performance for large SoC designs, reducing dependence on random initial solutions, and supporting FPGA P&R and runtime validation. The engineer will work in C/C++ on Linux/Unix, apply analytical and heuristic partitioning techniques, and collaborate with hardware verification and emulation teams.
