R&D Engineering, Manager at Synopsys

Synopsys is hiring an R&D Engineering Manager to lead the physical implementation of PVT Sensor IP across 1.4nm to 7nm foundry nodes. The role manages and mentors a team of ASIC physical design engineers, drives timing closure, power optimization, sign-off, project planning, resource allocation, and customer-facing delivery, and collaborates with front-end, verification, and product engineering teams. The position is based in Bangalore and Bhubaneswar and requires at least 10 years of ASIC or IP physical design experience, advanced-node design-flow expertise, and experience managing engineering teams.