Description
Synopsys is hiring an embedded memory design engineer to design and simulate SRAM, ROM, and register-file circuits using Cadence Virtuoso, support layout, perform bitcell characterization and reliability analysis, debug circuit issues, collaborate with CAD, verification, and frontend teams, and automate design tasks with C-Shell, Perl, or Python. The role focuses on delivering high-performance, power- and area-efficient memory IP for semiconductor products while building reusable design methodologies and improving cross-functional collaboration.
