RTL Design Engineer at Client’s Silicon Technology Engineering (STE), Digital ASIC Group

The RTL Design Engineer will develop mission-critical RTL for large mixed-signal ASICs in the Digital ASIC Group, collaborating with analog teams, product architects, verification, and physical design. Responsibilities include RTL specification and design, IP integration, test planning and debug support, timing constraints, STA, post-silicon lab bringup, and high-speed memory and serial design. The role requires a BSEE or MSEE, at least five years of experience, extensive Verilog RTL design experience, and familiarity with synthesis, CDC, STA, high-speed interfaces, and scripting tools.