RTL Design Engineer at sambanovasystems

Compensation

$120,000 – $200,000/yr

Location: San Jose, California
Type: Full-time
Level: senior
Posted: Aug 20, 2026

Description

SambaNova Systems is hiring an RTL Design Engineer to design and implement component blocks for the Reconfigurable Dataflow Unit (RDU) ASICs used in its AI acceleration systems. The role covers microarchitecture contributions, SystemVerilog RTL development and debugging, PPA optimization, synthesis, timing closure, quality checks, implementation through tape-out, and silicon bring-up, collaborating with architecture, verification, and physical design teams.

Required Skills

SystemVerilog
Computer architecture
PPA optimization
AXI/PCIe/Ethernet
Timing analysis
RTL verification
SystemVerilog Assertions
Python/Linux shell
Git

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
Required Previous Experiences: At least 5 years of ASIC RTL design experience
Preferred Qualifications: Master's or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
Full ASIC development cycle through tape-out and production silicon
AI workload acceleration
Low-power design, clock gating, and DVFS
Emulation or FPGA prototyping