Description
Snap Inc. is hiring an RTL Design Engineer for its Hardware IP design team to micro-architect, design, implement, debug, and optimize artificial intelligence hardware IPs for wearable devices. The role covers RTL design, gate-level synthesis, PPA optimization, regression and synthesis flows, code coverage, documentation, and collaboration with architecture, verification, neural-network, AI compiler, and operating-system teams. Candidates need an MSc in a related field or equivalent experience, at least five years of RTL hardware design and/or verification experience, and strong RTL, DfX, programming, and communication skills. The position follows a default-together approach requiring office attendance four or more days per week.
