Synopsys is seeking an experienced RTL Designer to join their testchip team in Ho Chi Minh City. This role involves designing and verifying DDRPHY/LPDDRR/HBM test chips using SystemVerilog/Verilog, collaborating with analog and mixed-signal teams, automating workflows with scripting languages, and debugging complex hardware issues. The successful candidate will contribute to delivering reliable, high-speed memory IP for next-gen platforms and enhance testchip team capabilities.
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