Description
River AI is hiring an RTL Design Engineer to architect and implement high-performance custom silicon for AI accelerators and related SoC components. The role covers architecture and micro-architecture, System Verilog RTL development, physical design integration, static timing analysis, and performance optimization across the compiler, hardware, and software stack. Candidates need a bachelor’s degree in Electrical or Computer Engineering, at least five years of advanced-node experience, and expertise in RTL, synthesis, physical design, and computer architecture. The position is based in Austin, Texas or Palo Alto, California, with an expected annual salary of $200,000 to $420,000 USD plus equity, visa sponsorship, and health, dental, vision, PTO, and relocation benefits.
