RTL Design Engineer – Memory Controller at ARM

Arm is hiring an RTL Design Engineer to design and implement one or more functional units of a Memory Controller. The role includes developing high-level specifications and micro-architecture plans, creating SystemVerilog RTL, collaborating with partners and verification teams, and debugging functional and performance issues. Candidates need a bachelor’s or master’s degree in Computer Science or Electrical/Computer Engineering, at least five years of experience in microprocessor, SoC, memory controller, or interconnect IP design, prior RTL design experience, and knowledge of DRAM and bus protocols. The position offers a hybrid work arrangement and a salary range of $198,100-$268,000 per year.