RTL Design Engineer – Wireless SoC at Tekfortune

Setup: Remote
Location: San Jose, California
Type: Contract
Level: senior
Posted: May 12, 2026

Description

Tekfortune is seeking an experienced RTL Design Engineer – Wireless SoC for a six-month remote engagement. The role focuses on designing, implementing, and verifying high-performance digital blocks for next-generation wireless SoCs, including DSP, interfaces, clock/reset, power management, debug logic, IP integration, PPA optimization, timing closure, and silicon bring-up. Candidates need at least five years of RTL design experience, strong SystemVerilog/Verilog and DSP hardware skills, and familiarity with SoC design flows, synthesis, simulation, STA, and DFT.

Required Skills

SystemVerilog/Verilog
DSP hardware
SoC design flows
Timing closure
DFT concepts
Debugging

Additional Information

Required Previous Experiences: 5+ years of hands-on RTL design experience using SystemVerilog or Verilog
Experience implementing DSP hardware, including filtering and FFT
Knowledge of SoC design flows, including CDC, power domains, timing constraints, and formal verification
Experience with synthesis, linting, simulation, and STA tools
Understanding of DFT concepts, including scan and BIST
Preferred Qualifications: Experience in wireless SoC domains such as Wi-Fi, cellular, mmWave, or satellite
RTL design of datapath, FIFO, DMA, arbitration, and AXI/AHB SoC buses
DSP modeling and RTL conversion using MATLAB, Python, or C++
Post-silicon debugging and chip bring-up experience
Exposure to analog-mixed-signal interfaces and calibration logic
Experience working in distributed or global team environments
Translation Company Name: Tekfortune