RTL Design Sr Staff Engineer at Synopsys

Synopsys is hiring a Senior Staff Digital IP Designer to develop high-speed mixed-signal PHY IP in SystemVerilog and Verilog. The role covers micro-architecture specification, RTL design through tape-out, design-quality checks, RTL and gate-level debugging, customer SoC integration and post-silicon support, and mentorship. It requires at least five years of ASIC RTL design experience, proficiency in SystemVerilog and Verilog, scripting experience, and strong communication skills. The position is based in Ha Noi, Da Nang, or Ho Chi Minh City.