Description
The role leads technical project work and manages customer technical queries while developing and maintaining RTL for digital blocks. Responsibilities include simulation and debugging, functional issue resolution, integration support, collaboration with verification and physical design teams, synthesis, linting, timing checks, and documentation. The position requires 4–12 years of RTL design experience using Verilog or SystemVerilog, along with digital electronics, simulation, ASIC design flow, EDA tools, version control, and communication skills.
