Description
Etched is hiring an RTL Intern to help design microarchitecture and implement logic in Verilog for machine-learning and frontier-intelligence hardware. The intern will contribute to RTL block development, participate in the full design cycle from microarchitecture discussions through synthesis and timing feedback, and work in a fast-paced, high-autonomy environment. The role is a 12-week paid internship based in San Jose, California, with housing support for relocating interns and daily meals in the office.
