RTL Logic Design Engineer at ARM

Compensation

$161,500 – $218,500/yr

Setup: Hybrid
Type: Full-time
Level: not_specified

Description

The candidate will join the System IP Coherent Interconnect design team responsible for developing highly scalable, configurable, flexible, high-performance, and powerful mesh to deliver significant bandwidth for hyperscale and AI infrastructure, while being power-efficient for IoT and automotive applications. This involves designing IP with optimal PPA, applying low-power design techniques, and collaborating with various engineering teams.

Required Skills

Fabric and Interconnect Design
High-Speed Interfaces
AMBA CHI
AXI
Transaction Ordering
Virtualization
MMUs
Cache Coherence
Host Bridge Functions

Additional Information

Required Previous Experiences: Experience in fabric and interconnect design.
Preferred Qualifications: Knowledge of transaction ordering, virtualization, MMUs, cache coherence, and host bridge functions.
History of high-quality, low-power, high-performance RTL logic design in reasonable timescales.
Experience with Lint, synthesis, static timing, and DFT.
Understanding of physical design and verification methods.
Experience with scripting languages like Perl, Ruby, etc., and competence with Unix/Linux, shells, and Makefiles.

About ARM

ARM

compute platformsCambridge, UK

Build the future of AI with Arm, with the most power-efficient, high-performance, and scalable compute platform. Trusted by top tech partners to drive innovation and unlock new possibilities.

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