Security Digital Design Engineer at Synopsys

Language

Location: Moreira
Level: not_specified
Posted: Sep 23, 2026

Description

Synopsys is hiring a Security IP Hardware Engineer in Porto to design and verify secure hardware IP cores using Verilog and SystemVerilog, UVM, and formal verification. The role involves translating security requirements into synthesizable hardware, building test environments, debugging RTL and simulation issues, collaborating with security engineers, and supporting specifications and customer integration. Candidates need strong RTL and ASIC verification experience, an MSc or PhD in a relevant technical discipline, and knowledge of IC design flows; hardware security or cryptographic IP experience is a plus. The position is part of Synopsys’ international Security IP team and offers health, wellness, and financial benefits.

Required Skills

RTL design
Verilog
SystemVerilog
UVM
Formal verification
ASIC verification
Hardware security
Debugging

Additional Information

Minimum Education: MSc or PhD in Electrical Engineering, Computer Science, or a related technical discipline
Required Previous Experiences: Hands-on RTL design experience writing synthesizable Verilog or SystemVerilog
ASIC verification experience using SystemVerilog, UVM, or Verilog in real project environments
UVM or formal verification experience
Preferred Qualifications: Experience with hardware security concepts or cryptographic IP
Translation Company Name: Synopsys