Description
Synopsys is hiring an ASIC Digital Design Engineer to design and verify secure hardware IP cores in Verilog and SystemVerilog. The role includes building UVM test environments, performing formal verification, collaborating with security and software engineers, and contributing to specifications and documentation. The position is based in Porto and requires an MSc or PhD in Electrical Engineering or Computer Science, at least three years of RTL design experience, and proficiency in ASIC verification and IC design flows.
