Description
Micron Technology is hiring a Principal Design Engineer for its NVEG (Non‑Volatile Engineering Group) to own and evolve timing-critical NAND datapath circuits between the NAND array and page buffer. The role covers scalable datapath architecture, clock and data timing, layout-aware design, SPICE/Fast-SPICE simulation, PVT and variability analysis, silicon correlation, root-cause debugging, design reviews, and cross-team technical leadership. Candidates need a BS or MS in Electrical Engineering, at least 8 years of relevant experience, and expertise in CMOS analog/mixed-signal design, high-speed datapath timing, layout parasitics, and simulation and debug.
