Description
NVIDIA is hiring a Physical Design Engineer for its Networking Silicon engineering team to perform advanced AI Static Timing Analysis on complex chiplet and full-chip designs. The role involves AI-assisted timing optimization and data analysis, building and debugging STA tools, using Prime Time and related signoff methodologies, identifying convergence risks, and owning the full timing closer from pre-layout through signoff. Candidates need a B.Sc. or M.Sc. in Electrical Engineering, at least five years of hands-on STA experience, Prime Time and signoff experience, and familiarity with AI tools or a willingness to learn.
