Description
NVIDIA is hiring a Senior Analog Layout Design Engineer to perform physical layout of mixed-signal functions such as PLLs, high-speed I/O, SerDes, general I/O, and ESD structures in sub-micron CMOS FinFET technologies using Cadence tools. The role collaborates with ASIC and mixed-signal engineers, performs floor planning and custom layout, verifies designs against rules and schematics, and conducts EM/IR analysis. Candidates need at least five years of relevant mask analog layout experience, an Electronics Practical Engineer certificate or B.Sc. in Electrical Engineering, knowledge of analog layout in submicron CMOS and FinFET technologies, expertise with Cadence Virtuoso, and experience with DRC and LVS verification tools.
