Senior ASIC Design Engineer - DFT at NVIDIA

Department: Engineer, ASIC

Compensation

$168,000 – $310,500/yr

Setup: On-site
Location: California
Type: Full-time
Level: senior
Posted: Sep 18, 2026

Description

NVIDIA is hiring a Senior ASIC Design Engineer for its DFT team to design, implement, and verify DFT IPs such as fuse controllers for next-generation SoC products. The role covers pre-silicon through post-silicon activities, including test planning, full-chip verification, ATE bring-up, debug, and issue resolution, while mentoring junior engineers. Candidates need a BS/MS in electrical or computer engineering or equivalent experience, at least 8 years of SoC architecture, RTL design, and verification experience, strong Verilog and DFT skills, and familiarity with ATE, scripting, and related semiconductor domains. The posting is marked hybrid and lists base salary ranges of 168,000–264,500 USD for Level 4 and 196,000–310,500 USD for Level 5, with applications accepted until September 22, 2026.

Required Skills

DFT IPs
Verilog RTL
UVM
ATE
Python
Failure analysis

Additional Information

Minimum Education: BS/MS in Electrical or Computer Engineering or equivalent experience in a related domain with proven DFT experience
Required Previous Experiences: 8+ years of hands-on experience in SoC architecture, RTL design, and verification
Experience in DFT design, methodology, and implementation
Experience in post-silicon bring-up on ATE, including pattern formats, test program development, and failure analysis
Preferred Qualifications: UVM experience
UVM-based verification environments
Fuse, eFuse, or on-chip security block design
DFT IP architecture across multiple product generations