Description

K2 is looking for a Senior ASIC Design Verification Engineer to join their team. The role involves verifying the functionality, performance, and robustness of custom silicon designs. Responsibilities include developing and executing verification plans, building SystemVerilog/UVM test benches, writing SVA assertions, driving testing strategies, running simulations, managing regression testing, participating in design reviews, collaborating with various engineering teams, supporting silicon bring-up, and conducting ASIC team interviews.

Required Skills

Verification
SystemVerilog/UVM test benches
SystemVerilog Assertions (SVA)
constrained-random and directed testing
simulations
coverage closure
regression testing
simulation farms
CI pipelines

Additional Information

Required Previous Experiences: Experience verifying the functionality, performance, and robustness of custom silicon designs.
Preferred Qualifications: Ability to define the verification approach and contribute to methodology development.
Strong collaboration skills with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers.
High ownership and deep technical engagement.
Opportunity to shape first-generation silicon.
Proficiency in building SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
Ability to write SystemVerilog Assertions (SVA) and integrate formal verification.
Expertise in driving constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
Experience in running simulations, triaging failures, driving root-cause analysis, and collaborating with RTL designers to resolve issues.
Skill in implementing and maintaining functional coverage, code coverage, assertion coverage, and ensuring coverage closure for sign-off.
Ability to manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
Involvement in design reviews, microarchitecture discussions, and influencing design-for-verification (DFV) best practices.
Collaboration with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
Support for silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
Participation in ASIC team interviews.
Motivated individual who thrives in a fast-paced environment
Excited about contributing to the success of a groundbreaking Series C space startup

About K2

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Senior ASIC Design Verification Engineer at K2

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About K2

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